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PreliminaryPL611
-30
Programmable Quick Turn Clock T M
FEATURES
* * * * * Advanced programmable PLL design Very low Jitter and Phase Noise (< 40ps Pk-Pk typical) Output frequency up to 375MHz CMOS. Supports differential CMOS output to produce PECL, LVDS inputs. Crystal inputs: o Fundamental crystal: 10MHz-30MHz o 3 RD overtone crystal: Up to 75MHz o Reference input: Up to 200MHz Accepts <1.0V reference signal input voltage One programmable I/O pin can be configured as Output Enable (OE), or Frequency Selection input (FSEL), or Reference clock. Single 3.3V 10% power supply Operating temperature range from -40C to 85C Available in 8-pin MSOP/SOIC, 6-pin SOT Green/ RoHS compliant packages.
PIN CONFIGURATION
XIN/FIN GND CLK0 CLK1
1
8
XOUT CLK2, OE, FSEL DNC VDD
PL611-30 SOP-8 MSOP-8
2 3 4
7 6 5
* * * * *
DESCRIPTION
The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink's Factory Programmable `Quick Turn Clock (QTC)' family. PhaseLink's PL611-30 product family can generate any output frequency up to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of up to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs.
BLOCK DIAGRAM
XIN/FIN XOUT
Xtal OSC FRef . R- counter Phase Detector M-counter ( 6 -bit) Charge Pump Loop Filter
Programming Logic
FSEL OE CLoad
FVCO = F Ref. * (2 * M /R)
P-counter (5-bit)
VCO
FOut = FVCO / (2 * P)
CLK[0:1] CLK2
Programmable Function
/1, /2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
PreliminaryPL611
-30
Programmable Quick Turn Clock T M
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ] Output Frequency
Fout = FIN * M / (R * P) where M= 6 bit R= 1 P= 5 bit 1. CLK[0:1]= VCO / 2 * P 2. CLK[2]= FIN or FIN/2
Output Drive Strength
Std: 10mA (default) High: 24mA
Crystal Load
Programmable Input/Output (pin #7)
# of Register Banks
2
Charge-Pump Current
4 levels of pump current setting
+/- 200ppm One output pin can be tuning. configured as 1. CLK2 = FIN or FIN/2 2. FSEL - input 3. OE - input
PIN DESCRIPTION Name
XIN/FIN GND CLK[0:1] VDD DNC
Pin # (M)SOP-8
1 2 3,4 5 6
Type
I P O P -
Description
Crystal or Reference input pin GND connection Programmable Clock Output [note:CLK0=~CLK1] VDD connection Do No Connect This programmable I/O pin can be configured as CLK2 (FIN or FIN/2) output, or OE input, or Frequency Selection (FSEL) input pin. This pin has an internal 60K pull up resistor. State 0 1 (default) OE Tristate CLK[0:1] Normal mode FSEL Select Bank '0' ROM Select Bank `1' ROM
CLK2, OE, FSEL
7
B
XOUT
8
O
Crystal output pin
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2
PreliminaryPL611
-30
Programmable Quick Turn Clock T M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Data Retention @ 85 C Soldering Temperature Storage Temperature Ambient Operating Temperature* TS -65 -40
SYMBOL
V DD VI VO
MIN.
MAX.
4.6 V DD +0.5 V DD +0.5 240 150 +85
UNITS
V V V Years C C C
-0.5 -0.5 -0.5
10
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency
CONDITIONS
Fundamental Crystal 3 rd Overtone Crystal At power-up (after VDD increases over 1.62V) Frequency vs. VDD+/-10% 15pF Load, 10/90%VDD, Standard drive 15pF Load, 10/90%VDD, High drive 15pF Load, 90/10%VDD, Standard drive 15pF Load, 90/10%VDD, High drive At VDD/2 Equal loading (15 pF). Equal frequency & drive strength With capacitive decoupling between VDD and GND. Operating only one output.
MIN.
10
TYP.
MAX.
30 75 10
UNITS
MHz MHz ms ppm ns ns ns ns % ps
Settling Time VDD Sensitivity Output Rise Time
-2 2.5 1.0 2.5 1.0 45 50
2 3.5 1.5 3.5 1.5 55 500
Output Fall Time Duty Cycle Max. output skew between same frequency clocks Period Jitter, peak-to-peak* (measured from 10,000 samples)
40
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 3
PreliminaryPL611
-30
Programmable Quick Turn Clock T M
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded Outputs Operating Voltage Output Low Voltage Output High Voltage Output Current Short-circuit Current
SYMBOL
IDD VDD VOL VOH IOSD IOHD IS
CONDITIONS
At 10MHz, load=15pF
MIN.
TYP.
MAX.
15
UNITS
mA V V V
2.25 IOL = +4mA (Standard drive) IOH = -4mA (Standard drive) VOL = 0.4V, VOH = 2.4V (Standard drive) VOL = 0.4V, VOH = 2.4V (High Drive) VDD - 0.4 10 24 50
3.63 0.4
mA mA mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency 3rd Overtone Crystal Resonator Frequency Crystal Loading Rating (The IC can be programmed for any value in this range.) Maximum Sustainable Drive Level Operating Drive Level Crystal Shunt Capacitance Effective Series Resistance, Fundamental, 10-30MHz Effective Series Resistance, [CO< 4pF, CL=5pF/8pF] 3 rd Overtone, 30-50MHz C0 RS ESR ESR ESR 100 6 30 100/70 60/40 45/30
SYMBOL
FXIN FXIN CL (xtal)
MIN.
10
TYP.
MAX.
30 75
UNITS
MHz MHz pF W W pF
5
20 500
Effective Series Resistance, 3 rd Overtone, 50-65MHz, [CO< 4pF, CL=5pF/8pF] Effective Series Resistance, 3 rd Overtone, 65-75MHz [CO< 4pF, CL=5pF/8pF
Note: A detailed crystal specification document is also available for this part
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 4
PreliminaryPL611
-30
Programmable Quick Turn Clock T M
Figure 1 below describes how to terminate the differential CMOS outputs of PhaseLink's PL611-30 Programmable QTC clock for use with PECL or LVDS inputs. The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination scheme you can use the PL611-30 for all your LVDS and PECL clock requirements up to 375MHz.
+3.3V CMOS Output R1 50 line R2 Input
R3 Complementary CMOS Output R1 50 line
R3
Complementary Input PECL LVDS 2.35V 1.40V 1.59V 1.10V
3.3V 0V Component selection For PECL input For LVDS input R1 = 130 R2 = 82 R3 = 130 R1 = 360 R2 = 82 R3 = 130
R2 +3.3V
Notes: Place R1 as close to the CMOS outputs as possible. Place R2 and R3 as close to the PECL/LVDS inputs as possible.
Figure 1
The above layout allows the PL611-30 to drive either a PECL or LVDS input by simply changing the value of R1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5
PreliminaryPL611
-30
Programmable Quick Turn Clock T M
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
MSOP 8L Symbol A A1 A2 B C D E H L e SOP 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC Dimension in MM Min. Max. --1.10 0.05 0.15 0.81 0.91 0.25 0.40 0.13 0.23 2.90 3.10 2.90 3.10 4.90 BSC 0.445 0.648 0.65 BSC
E
H
D
A2 A A1 e b C L
E
H
D
A2 A A1 e b C L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 6
PreliminaryPL611
-30
ORDERING INFORMATION
Programmable Quick Turn Clock T M
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PL611-XXX
PART NUMBER 3 DIGIT ID Code *
X X-R
NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I = INDUSTRIAL
PACKAGE TYPE S=SOIC M=MSOP
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number. * PhaseLink offers Green Package Only for this product family.
Part / Order Number PL611-30-XXXSC PL611-30-XXXSC-R PL611-30-XXXMC PL611-30-XXXMC-R
Marking C3XXX C3XXX C3XXX C3XXX
Package Option 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin MSOP (Tube) 8-Pin MSOP (Tape and Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 7

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